Please refer to FIG. 1, which is the schematic diagram showing the first conventional scheme for writing the data DR1 to the double data rate synchronous dynamic random access memory (DDR SDRAM) array 101. FIG. 1 shows a memory device 10 and waveforms including the clock signal CLK1, the data strobe signal DQS1, the data bus signal DQ1 and the signal DAR11. The memory device 10 receives the clock signal CLK1, the data strobe signal DQS1 and the data bus signal DQ1, and includes the DDR SDRAM array 101 operating in synchronization with the clock signal CLK1. The clock signal CLK1 has the rising edge RC11 and the rising edge RC12 lagged behind the rising edge RC11 by one clock cycle of the clock signal CLK1. The data bus signal DQ1 includes the data DR1.
Based on DDR/DDR2/DDR3 JEDEC timing specification, both the data DR1 and the rising edge of the data strobe signal DQS1 corresponding to the rising edge RC 12 can arrive at the memory device 10 anytime between ¼ clock cycle before and ¼ clock cycle after the rising edge RC12. The data DR1 is provided to the memory device 10 on the rising edge of the data strobe signal DQS1 corresponding to the rising edge RC12. If the data strobe signal DQS1 is coming in the memory device 10 later than the clock signal CLK1, the data strobe signal DQS1 is shown to be the signal DQS11 and the data DR1 is shown to be the data DR1L. If the data strobe signal DQS1 is coming in the memory device 10 earlier than the clock signal CLK1, the data strobe signal DQS1 is shown to be the signal DQS12 and the data DR1 is shown to be the data DR1E.
The signal DQS11 includes the rising edge RDL11 corresponding to the rising edge RC12. The signal DQS12 includes the rising edge RDE11 corresponding to the rising edge RC12. The rising edges RDL11 and RDE11 are coming in later and earlier respectively than the rising edge RC12. The rising edges RDL11 and RDE11 respectively correspond to the data DR in duration HR1L and the data DR1E in duration HR1E, and are used to respectively capture the data DR and the data DR1E.
The signal DAR11 is produced in response to the data strobe signal DQS1 and the data bus signal DQ1. The data DR1 of the data bus signal DQ1 is latched into the signal DAR11 at a first time point lagged behind the rising edge of the data strobe signal DQS1, corresponding to the rising edge RC12, by a first time interval until a second time point in response to the rising edge of the data strobe signal DQS1 corresponding to the rising edge RC12.
As shown in FIG. 1, the data DR1 and the rising edge RDL11 arrive at the memory device 10 at a time point of ¼ clock cycle after the rising edge RC12. The rising edge RDL11 is used to capture the data DR1L, and the data DR1L is latched into the signal DAR11 at the time point TR11 lagged behind the rising edge RDL11 by the time interval GR1 until the time point TR12 in response to the rising edge RDL11. The time intervals GR1 is a propagation delay from the rising edge RDL11 to output the data DR1L-RDL11 of a flip-flop or a latch (not shown) being used to capture the data DR1L. The time point TR11 and the time point TR12 have the duration HR11 being one clock cycle of the clock signal CLK1.
As shown in FIG. 1, the data DR1E and the rising edge RDE11 arrive at the memory device 10 at a time point of ¼ clock cycle before the rising edge RC12. The rising edge RDE11 is used to capture the data DR1E, and the data DR is latched into the signal DAR 11 at the time point TR21 lagged behind the rising edge RDE11 by the time interval GR2 until the time point TR22 in response to the rising edge RDE11. The time intervals GR2 is a propagation delay from the rising edge RDE11 to output the data DR1E-RDE11 of the flip-flop or the latch being used to capture the data DR1E. The time point TR21 and the time point TR22 have the duration HR12 being one clock cycle of the clock signal CLK1. For instance, the time intervals GR1 and GR2 have a same time length.
The internal clock signal ICLK1 is produced, e.g. by an input buffer (not shown) in the memory device 10, in response to the clock signal CLK1, and is provided to the inside of the memory device 10. The data valid window QR1 of the data DR1, seen by the internal clock ICLK1, is a time interval between the time point TR11 and the time point TR22. Therefore, the data valid window QR1 is only a ½ clock cycle of the clock signal CLK1.
Please refer to FIG. 2, which is the schematic diagram showing the second conventional scheme for writing the data DF1 to the double data rate synchronous dynamic random access memory (DDR SDRAM) array 101. FIG. 2 shows waveforms including the clock signal CLK1, the data strobe signal DQS1, the data bus signal DQ1 and the signal DAF11. The clock signal CLK1 has the falling edge FC11 and the falling edge FC12 lagged behind the falling edge FC11 by one clock cycle of the clock signal CLK1. The data bus signal DQ1 includes the data DF1.
Based on DDR/DDR2/DDR3 JEDEC timing specification, both the data DF1 and the falling edge of the data strobe signal DQS1 corresponding to the falling edge FC12 can arrive at the memory device 10 anytime between ¼ clock cycle before and ¼ clock cycle after the falling edge FC12. The data DF1 is provided to the memory device 10 on the falling edge of the data strobe signal DQS1 corresponding to the falling edge FC12. If the data strobe signal DQS1 is coming in the memory device 10 later than the clock signal CLK1, the data strobe signal DQS1 is shown to be the signal DQS11 and the data DF1 is shown to be the data DF1L. If the data strobe signal DQS1 is coming in the memory device 10 earlier than the clock signal CLK1, the data strobe signal DQS1 is shown to be the signal DQS12 and the data DF1 is shown to be the data DF1E.
The signal DQS11 includes the falling edge FDL11 corresponding to the falling edge FC12. The signal DQS12 includes the falling edge FDE11 corresponding to the falling edge FC12. The falling edges FDL11 and FDE11 are coming in later and earlier respectively than the falling edge FC12. The falling edges FDL11 and FDE11 respectively correspond to the data DF1L in duration HF1L and the data DF1E in duration HF1E, and are used to respectively capture the data DF1L and the data DF1E.
The signal DAF11 is produced in response to the data strobe signal DQS1 and the data bus signal DQ1. The data DF1 of the data bus signal DQ1 is latched into the signal DAF11 at a third time point lagged behind the falling edge of the data strobe signal DQS1, corresponding to the falling edge FC12, by a second time interval until a fourth time point in response to the falling edge of the data strobe signal DQS1 corresponding to the falling edge FC12.
As shown in FIG. 2, the data DF1 and the falling edge FDL11 arrive at the memory device 10 at a time point of ¼ clock cycle after the falling edge FC12. The falling edge FDL11 is used to capture the data DF1L, and the data DF1L is latched into the signal DAF11 at the time point TF11 lagged behind the falling edge FDL11 by the time interval GF1 until the time point TF12 in response to the falling edge FDL11. The time intervals GF1 is a propagation delay from the falling edge FDL11 to output the data DF1L-FDL11 of a flip-flop or a latch (not shown) being used to capture the data DF1L. The time point TF11 and the time point TF12 have the duration HF11 being one clock cycle of the clock signal CLK1.
As shown in FIG. 2, the data DF and the falling edge FDE11 arrive at the memory device 10 at a time point of ¼ clock cycle before the falling edge FC12. The falling edge FDE11 is used to capture the data DF1E, and the data DF is latched into the signal DAF11 at the time point TF21 lagged behind the falling edge FDE11 by the time interval GF2 until the time point TF22 in response to the falling edge FDE11. The time intervals GF2 is a propagation delay from the falling edge FDE11 to output the data DF1E-FDE11 of the flip-flop or the latch being used to capture the data DF1E. The time point TF21 and the time point TF22 have the duration HF12 being one clock cycle of the clock signal CLK1. For instance, the time intervals GF1 and GF2 have a same time length. The data valid window QF1 of the data DF1, seen by the internal clock ICLK1, is a time interval between the time point TF11 and the time point TF22. Therefore, the data valid window QF1 is only a ½ clock cycle of the clock signal CLK1.
Because the data valid windows QR1 and QF1 for writing the data DR1 and the data DF1 to the DDR SDRAM array 101 are small, capturing the data DR1 and the data DF1 properly can be difficult especially with wide process, temperature and voltage variations, so that it is very difficult to meet JEDEC DQS and Data timing requirement.